/**
 * @file	flash.c
 * @author	chipsea
 * @brief	
 * @version	0.1
 * @date	2020-11-30
 * @copyright Copyright (c) 2020, CHIPSEA Co., Ltd.
 * @note
 */

/*******************************************************************************
* @file		flash.h
* @brief	Contains all functions support for flash driver
* @version	0.0
* @date		27. Nov. 2017
* @author	qing.han
* 

*
*******************************************************************************/
#ifndef _FLASH_H_
#define _FLASH_H_

#include "rom_sym_def.h"
#include "clock.h"
#include "types.h"
#include "gpio.h"
#include "version.h"

#define FLASH_SIZE_256KB        (0)
#define FLASH_SIZE_512KB        (1)
#define FLASH_SIZE_1MB          (2)

#define SPIF_FLASH_SIZE         FLASH_SIZE_512KB

#define SPIF_TIMEOUT            (0x7ffffff)//1000000

#define SFLG_WIP    1
#define SFLG_WEL    2
#define SFLG_WELWIP 3

//define flash ucds
#define FLASH_BASE_ADDR         (0x11000000)
#define FLASH_UCDS_ADDR_BASE    0x11005000

#define CHIP_ID_LENGTH          64
#define CHIP_ID_PID_LEN         16
#define CHIP_ID_LID_LEN         10
#define CHIP_ID_MID_LEN         16
#define CHIP_ID_TID_LEN         14
#define CHIP_ID_SID_LEN         8

#define CHIP_MADDR_LEN          6

//xip flash read instrcution
#define XFRD_FCMD_READ          0x0000003
#define XFRD_FCMD_READ_DUAL     0x801003B
#define XFRD_FCMD_READ_QUAD     0x801006B


#define FCMD_RESET              0x99  //reset
#define FCMD_ENRST              0x66  //enable reset
#define FCMD_WREN               0x06  //write enable
#define FCMD_WRDIS              0x04  //write disable
#define FCMD_VSRWREN            0x50  //Volatile SR Write Enable


#define FCMD_CERASE             0x60  //(or 0xC7)chip erase
#define FCMD_SERASE             0x20  //sector erase
#define FCMD_BERASE32           0x52  //block erease 32k
#define FCMD_BERASE64           0xD8

#define FCMD_DPWRDN             0xB9  //deep power down
#define FCMD_RLSDPD             0xAB  //release from powerdown(and read device id)
#define FCMD_WRST               0x01  //write status
#define FCMD_RDID               0x9F  //read ID
#define FCMD_RDST               0x05  //read status
#define FCMD_RDST_H             0x35  //read status high byte
#define FCMD_PPROG              0x02  //page program
#define FCMD_READ               0x03  //read
#define FCMD_READF              0x0B  //fast read
#define FCMD_READDO             0x3B  //dual output fast read
#define FCMD_READDIO            0xBB  //dual I/O fast read
#define FCMD_READQO             0x6B  //quad output fast read
#define FCMD_READQIO            0xeB  //quad I/O fast read
#define FCMD_READQIOW           0xe7  //quad I/O fast read word

//Flash address definition
#define FLASH_CHIP_INFO_ADDR				0x0000
#define FLASH_1ST_BOOT_INFO_ADDR			0x2000
#define FLASH_APP_BOOT_INFO_ADDR			0x3000
#define FLASH_PROGRAMMER_INFO_ADDR			0x4000
#define FLASH_APP_ADDR						0x5000
#define FLASH_CODE_BACKUP_ADDR				0x38000				
#define FLASH_BOOTLOADER_ADDR				0x6b000	//64KB
#define FLASH_BOOTLOADER_UPDATE_INFO_ADDR	0x7b000	//0x7b000~0x7bfff	4KB 

typedef enum{
    FLASH_LOCK_504K = 0x04,//0x00-0x7DFFF
    FLASH_LOCK_496K = 0x08,//0x00-0x7BFFF
    FLASH_LOCK_480K = 0x0C,//0x00-0x77FFF
    FLASH_LOCK_448K = 0x10,//0x00-0x6FFFF
    FLASH_LOCK_384K = 0x14,//0x00-0x5FFFF
    FLASH_LOCK_HALF = 0x18,//0x00-0x3FFFF
    FLASH_LOCK_ALL = 0x1C,//0x00-0x7FFFF
    FLASH_UNLOCK = 0x00,
} flash_lock_t;

ErrCode_t HalFlashInit(void);
void HalFlashRead(uint32_t addr, uint8_t *buf, uint32_t len);
ErrCode_t HalFlashWrite(uint32_t addr, uint8_t* buf, uint32_t len);
ErrCode_t HalFlashWriteByDma(uint32_t addr, uint8_t* buf, uint32_t len);
ErrCode_t HalFlashErase(uint32_t sectorNum);
ErrCode_t HalFlashWriteWord(uint32_t addr, uint32_t value);
// void HalFlashLock(flash_lock_t lock);
// void HalFlashUnlock(void);

#endif








